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march 20, 1997 5:12 pm page 1 of 13 mc68302 document table 1: # spec no. description spec name um 33mhz min 33mhz max 1 1 cycle period tcyc 30 2 2,3 clock pulse width tcl,tch 15 3 5a extal to clock delay tcd 2 11 4 6 clock high to fc, address valid tchfcadv 0 27 5 7 clock high to address, data hi-z tchadz - 25 6 8 clock high to address, fc invalid (minimum) tcha 0 - 7 9 clock high to as, ds asserted tchsl 3 15 8 11 address, fc valid to as, ds assert (read) as assert (write) tafcvsl 8 - 9 12 clock low to as, ds negate tclsn - 15 10 13 as, ds negated to address fc invalid tsha 8 - 11 14 as (and ds read) width asserted tsl 60 - 12 14a ds width asserted, write tdsl 30 - 13 15 as, ds width negate tsh 30 - 14 16 clock high to control bus hi-z tchca - 25 15 17 as, ds negated to r/w invalid tshrh 8 - 16 18 clock high to r/w hi tchrh - 15 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 2 of 13 mc68302 document 17 20 clock high to r/w lo tchrl - 15 18 20a as asserted to r/w low (write) tasrv - 7 19 21 address fc valid to r/w low (write) tafcvrl 8 - 20 22 r/w low to ds assert (write) trasa 21 23 clock low to data valid tcldo - 15 22 25 as, ds negated to data-out invalid tcldo - 15 23 26 data-out valid to ds asserted (write) tdosl 8 - 24 27 data in to clock low tdicl 4 - 25 28 as, ds negate to dtack negate tshdah 0 65 26 29 as, ds negated to data in invalid tshdii 0 - 27 30 as, ds negated to berr negated tshbeh 0 - 28 31 dtack assert to data-in valid tdaldi - 25 29 32 halt,reset in transition time trhr, trhf - 150 30 33 clock high to bg assert tchgl - 15 31 34 clock high to bg negate tchgh - 15 32 35 br assert to bg assert tbrlgl 2.5 clks 4.5 clks 33 36 br negate to bg negate tbrhgh 1.5 clks 2.5 clks table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 3 of 13 mc68302 document 34 37 bgack assert to bg negate tgalgh 2.5 clks 4.5 clks 35 37a bgack assert to br negate tgalbrh 10 ns 1.5 clks 36 38 bg assert to addr, data, etc. hi-z tglz - 25 37 39 bg width negate tgh 1.5 clks - 38 40 bgack assert to address valid tgalav 15 - 39 41 bgack assert to as assert tgalasa - 20 40 44 as, ds negate to avec negate tshvph 0 25 41 46 bgack width low tgal 1.5 clks 1.5 clks 42 47 async input setup time tasi 7 - 43 48 berr assert to dtack assert tbeldal 7 - 44 53 data-out hold from clk high tchdoi 0 - 45 55 r/w assert to data bus impedance change trldbd 0 - 46 56 halt/reset pulse width thrpw 10 clks - 47 57 bgack negate to as, ds, rw driven tgasd 1.5 clks - 48 57a bgack negate to fc tgafd 1 clk - 49 58 br negate to as, ds, rw driven trhsd 1.5 clks - 50 58a br negate to fc trhfd 1 clk table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 4 of 13 mc68302 document 51 60 clock high to bclr assert tchbca - 15 52 61 clock high to bclro hi-z tchbcn - 15 53 62 clock low to rmc assert tclrml - 17 54 63 clock high to rmc negate tchrmh - 17 55 64 rmc negate to bg assert trmhgl - 15 56 80 dreq asynchronous set up time treqasi 10 - 57 81 dreq width low treql 2 clks - 58 82 dreq low to br low treqlbrl - 2 clks 59 83 clock high to br low tchbrl - 15 60 84 clock high to br hi-z tchbrz - 15 61 85 bgack low to br hi-z tbklbrz 15 - 62 86 clock high to bgack low tchbkl - 15 63 87 as and bgack high to bgack low tabhbkl 1.5 clks 2.5 clks + 20 ns 64 88 bg low to bgack low tbglbkl 1.5 clks 2.5 clks + 20 ns 65 89 br hi-z to bg high trhbgh 0 - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 5 of 13 mc68302 document 66 90 clock on which bgack low to clock on which as low tclbklal 2 clks 2 clks 67 91 clock high to bgack high tchbkh - 15 68 92 clock low to bgack hi-z tclbkz - 10 69 93 clock high to dack low tchackl - 15 70 94 clock low to dack high tclackh - 15 71 95 clock high to done low (output) tchdnl - 15 72 96 clock low to done hi-z tcldnz - 15 73 97 done input low to clock high tdnltch 10 - 74 100 rw valid to ds low trwvdsl 0 - 75 101 ds low to data-in valid tdsldiv - 15 76 102 dtack low to data in hold time tdkldh 0 - 77 103 as valid to ds low tasvdsl 0 - 78 104 dtack low to as, ds high tdkldsh 0 - 79 105 ds high to dtack high tdshdkh - 25 80 106 ds inactive to as inactive tdsiasi 0 - 81 107 ds high to rw high tdshrwh 0 - 82 108 ds high to data hi-z tdshdz - 25 table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 6 of 13 mc68302 document 83 108a ds high to data out hold time tdshdh 0 - 84 109a data out valid to dtack low tdovdkl 10 - 85 110 address valid to as low tavasl 8 - 86 111 as low to clock high taslch 15 - 87 112 clock low to as high tclash - 25 88 113 as high to address hold time on write tashah 0 - 89 114 as inactive time tash 1 clk - 90 115 uds/lds low to clock high tslch 21 - 91 116 clock low to uds/lds high tclsh - 20 92 117 rw valid to clock high trwvch 15 - 93 118 clock high to rw high tchrwh - 20 94 119 as low to iac high tasliah - 21 95 120 as high to iac low tashial - 21 96 121 as low to dtack low (0 wait states) tasldtl - 25 97 122 clock low to dtack low (1 wait state) tcldtl - 15 98 123 as high to dtack high tashdth - 20 99 124 dtack high to dtack hi-z tdthdtz - 10 table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 7 of 13 mc68302 document 100 125 clock high to data out valid tchdov - 15 101 126 as high to data hi-z tashdz - 25 102 127 as high to data out hold time tashdoi 0 - 103 128 as high to address hold time on read tashai 0 - 104 129 uds/lds inactive time tsh 1 clk - 105 130 data in valid to clock low tcldiv 15 - 106 131 clock low to data in hold time tcldih 10 - 107 140 clock high to iac high tchiah - 21 108 141 clock low to iac low tclial 21 109 142 clock high to dtack low tchdtl - 25 110 143 clock low to dtack high tcldth - 22 111 144 clock high to data out valid tchdov - 15 112 145 as high to data out hold time tashdoh 0 - 113 150 clock high to cs, iack low tchcsiakl 0 20 114 151 clock low to cs, iack high tclcsiakh 0 20 115 152 cs width negated tcsh 30 - 116 153 clock high to dtack low (0 wait states) tchdtkl - 25 table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 8 of 13 mc68302 document 117 154 clock low to dtack low (1-6 wait states) tcldtkh - 15 118 155 clock low to dtack high tcldtkh - 20 119 156 clock high to berr low tchberl - 20 120 157 clock low to berr hi-z tclberh - 20 121 158 dtack high to dtack hi-z tdtkhdtkz - 10 122 160 as low to cs low taslcsl - 16 123 161 as high to cs high tashcsh - 16 124 162 address valid to as low tavasl 8 - 125 163 rw valid to as low trwvasl 8 - 126 164 as negated to address hold time tashai 0 - 127 165 as low to dtack low (0 wait states) tasldtkl - 25 128 167 as high to dtack high tashdtkh - 18 129 168 as low to berr low taslberl - 18 130 169 as high to berr hi-z tashberh - 18 131 171 input data hold time from s6 low tidhcl 5 - 132 172 cs negated to data out invalid (write) tcsndoi 7 - 133 173 address, fc valid to cs asserted tafvcsa 15 - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 9 of 13 mc68302 document 134 174 cs negated to address, fc invalid tcsna 12 - 135 175 cs low time (0 wait states) tcslt 60 - 136 176 cs negate to rw invalid tcsnrwi 7 - 137 177 cs assert to rw low (write) tcsarwl - 8 138 178 cs negate to data in invalid tcsndii 0 - 139 180 input data setup time tdsu 14 - 140 181 input data hold time tdh - 19 141 182 clock high to data out valid tchdov - 20 142 190 interrupt pulse width low irq tipw 28 - 143 191 minimum time between active edges taemt 3 clks - 144 200 timer input capture pulse width ttpw 28 - 145 201 tin clock low pulse width tticlt 28 - 146 202 tin clock high pulse width and input capture high pulse width tticht 2 clks - 147 203 tin clock cycle time tcyc 3 clks - 148 204 clock high to tout valid tchtov - 24 149 205 frz input setup time (to clock high) tfrzsu 14 - 150 206 frz input setup time (from clock high) tfrzht 7 - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 10 of 13 mc68302 document 151 250 spclk clock output period 4 clks 64 clks 152 251 spclk clock output rise/fall time 0 6 153 252 delay from spclk to transmit 0 20 154 253 scp receive setup time 20 - 155 254 scp receive hold time 6 - 156 260 l1clk (idl clock) frequency - 13.3 mhz 157 261 l1clk width low 28 - 158 262 l1clk width high p+10 - 159 263 l1txd, l1rq, sds1-sds2 rise/fall time - 12 160 264 l1sy1 (sync) setup time (to l1clk falling edge) 15 - 161 265 l1sy1 (sync) hold time (to l1clk falling edge) 28 - 162 266 l1sy1 (sync) inactive before 4th l1clk 0 - 163 267 l1txd active delay (from l1clk falling edge) 0 40 164 268 l1txd to hi-z (from l1clk rising edge) 0 26 165 269 l1rxd setup time (to l1clk falling edge) 26 - 166 270 l1rxd hold time (from l1clk falling edge) 26 - 167 271 time between successive idl syncs 20 l1clks - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 11 of 13 mc68302 document 168 272 l1rq valid before falling edge of l1sy1 1 l1clks - 169 273 l1gr setup time (to l1sy1 falling edge) 26 - 170 274 l1gr hold time (from l1sy1 falling edge) 26 - 171 275 sds1-sds2 active delay from l1clk rising edge 7 40 172 276 sds1-sds2 inactive delay from l1clk falling edge 7 40 173 280 l1clk clock period normal mode 1800 2100 174 281 l1clk width low/high normal mode 840 1450 175 282 l1clk rise/fall time normal mode - - 176 280 l1clk clock period mux mode 150 - 177 281 l1clk width low/high mux mode 55 - 178 281a l1clk width high mux mode p+10 - 179 282 l1clk rise/fall time mux mode - - 180 283 l1sy1 sync setup time to l1clk falling edge 15 - 181 284 l1sy1 sync hold time (from l1clk falling edge) 26 - 182 285 l1txd active delay (from l1clk rising edge) 0 55 183 286 l1txd active delay (from l1sy1 rising edge) 0 55 184 287 l1rxd setup time to l1clk rising edge 14 - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 12 of 13 mc68302 document 185 288 l1rxd hold time from l1clk rising edge 26 - 186 289 time between successive l1sy1 64 l1clk 192 l1clk - - 187 290 sds1-sds2 active delay from l1clk rising edge 7 45 188 291 sds1-sds2 active delay from l1sy1 rising edge 7 45 189 292 sds1-sds2 inactive delay from l1clk falling edge 7 45 190 293 gcidcl (gci data clock) active delay 0 26 191 300 l1clk (pcm clock) frequency - 13.2 mhz 192 301 l1clk width low 27 - 193 301a l1clk width high p+10 - 194 302 l1sy0-l1sy1 setup time 0 - 195 303 l1sy0-l1sy1 hold time 20 - 196 304 l1sy0-l1sy1 width low 1 l1clk - 197 305 time between successive sync signals 8 l1clk - 198 306 l1txd data valid after l1clk rising edge 0 40 199 307 l1txd to hi-z (from l1clk rising edge) 0 26 200 308 l1rxd setup time (to l1clk falling edge) 11 - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
march 20, 1997 5:12 pm page 13 of 13 mc68302 document 201 309 l1rxd hold time (from l1clk falling edge) 26 - 202 315 rclk1 and tclk1 frequency internal clk external clk - - 11 mhz 13.2 mhz 203 316 rclk1 and tclk1 low internal clk external clk 35ns p+10 - - 204 316a rclk1 and tclk1 high internal clk external clk 35 25 - - 205 317 rclk1 and tclk1 rise/fall time internal clk external clk - - 11 - 206 318 rxd1 active delay from tclk1 falling edge internal clk external clk 0 0 20 30 207 319 rts1 active/inactive delay from tclk1 falling edge internal clk external clk 0 0 20 50 208 320 cts1 setup time to tclk1 rising edge internal clk external clk 30 7 - - 209 321 rxd1 setup time to rclk1 rising edge internal clk external clk 30 7 - - 210 322 rxd1 hold time from rclk1 rising edge internal clk external clk 7 30 - - 211 323 cd1 setup time to rclk1 rising edge internal clk external clk 30 7 - - table 1: # spec no. description spec name um 33mhz min 33mhz max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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